1. Technical Field
The present invention generally relates to electrical circuit design verification systems and in particular to the application of historical verification data in electrical circuit design verification systems.
2. Description of the Related Art
The increasing complexity of modem hardware designs dictates that extremely rigorous functional verification practices are necessary to flush out the majority of circuit design flaws. These verification practices take on many forms, from the running of extensive simulation “regression buckets” that test the design behavior under specific conditions, to more exhaustive semi-formal or formal verification techniques that are executed to determine complete design correctness. Overall, the verification process requires exponential resources with respect to design size. Formal verification therefore tends to be applicable only to smaller designs, and even then run times easily may consume hours, days, or months. Incomplete verification techniques such as simulation and semi-formal approaches consume lesser computational resources and are, thus, scalable to much larger designs. Nevertheless, in order to obtain as much coverage as possible from these incomplete techniques, these verification techniques are often extensively deployed, collectively requiring hours, days or even months of run-time.
One intrinsic design characteristic that complicates the verification process is that the verification process may have to be performed more than once on a given design. The verification process may be performed multiple times because the design evolves many times during the development phase when new functionality is entered, design flaws are rectified, synthesis optimizations are performed on the design to meet timing/size constraints, and pervasive functions are added such as test logic. Despite how small a change may be, unless the change is demonstrated to be very trivial, it is often necessary to re-perform the verification process anew every time the design changes. Multiple runs of the verification process may be a particular bottleneck in the case of a very late design change as in a change that occurs immediately before design fabrication.